HDL implementation of an ASIC testing interface

Modern comunication standards exploit wide bandwidth and complex modulation schemes to provide high data throughput. 

The goal of the project is to implement an interface between a custom CMOS Integrated circuit prototype of wide-band Analog to Digital Converter (ADC) and a general purpose workstation in order to provide a debug tool during the ASIC characterization and validation campaign.

Area di ricerca

Automated Hardware Testing, High speed Analog to Digital Converter, Custom Integrated Circuit.

Tecnologie da utilizzare

VHDL, Python, MATLAB

Docente

Luca Bertulessi

Termine per accettazione progetto

20/02/2025

Keyword (max 3 separate da virgola)

Hardware interfaces, High speed Analog to Digital Converter, Custom Integrated Circuit.

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